1. Field of the Invention
The present invention relates to a level shift circuit which can be used in peripheral driving circuits of a liquid crystal display (LCD) apparatus.
2. Description of the Related Art
In an LCD apparatus, peripheral driving circuits such as a gate bus line driving circuit (scan bus line driving circuit and a drain bus line driving circuit (data bus line driving circuit) are manufactured on the same substrate of an LCD panel of an active matrix type, so that the LCD apparatus can be small in size and is low in cost.
The above-mentioned driving circuits are conventionally formed by using polycrystalline silicon thin film transistors (TFTs), and therefore, the driving power of the driving circuits is low. On the other hand, an external clock signal supplied to the driving circuits conventionally has a low level such as 3.3 V or 5 V. The driving circuits cannot be operated directly by such a low clock signal. In other words, a voltage pull-up circuit on a level shift circuit is required as an interface between an external signal receiving circuit (terminal) for receiving such an external clock signal and the driving circuits.
A prior art level shift circuit is formed by a CMOS inverter for receiving an input voltage and generating two-phase output signals and a CMOS level shifter operated by the two-phase output signals.
In this case, the CMOS inverter is powered by a plower supply voltage which is, for example, 3.3 V, and a lower supply voltage which is 0 V. Also, the CMOS level shifter is powered by a power supply voltage which is, for example, 12 V, and the power supply voltage 0 V.
Further, in order to increase the operation speed, the size of N-channel MOS transistors of the CMOS level shifter is made much larger than that of P-channel MOS transistors thereof (see FIG. 1 of JP-50-151433). This will be explained later in detail.
In the prior art level shift circuit, however, if the transistors are formed by polycrystalline silicon TETs, the absolute value of the threshold voltage of the P-channel MOS transistors and the threshold voltage of the N-channel MOS transistors cannot be about 2 V or less than 2 V, due to the grain boundaries of polycrystalline silicon and a low-temperature chemical vapor deposition (CVD) process. As a result, the level shift circuit cannot normally operate.